I am a Semiconductor Research Engineer with more than 10 years of experience in R&D projects related with static and dynamic measurements, characterization and device modeling of various commercial and research oriented CMOS and wide bandgap processes. Deep understanding of semiconductor devices’ operation and performance issues.

• Extensive hands-on experience setting-up and performing on-wafer DC,CV and RF measurements.
• Design oriented characterization and modeling of CMOS technology node’s statistical behavior. 
• Utilizing high level languages for modeling and characterization purposes (ex. Java application for modeling and characterization (MOSGUI project), measurement and data acquisition lab setups using PyVISA).
• Extensive experience in commercial and open-source simulators (ex. NGSPICE, Cadence Spectre) and EDA tools (ex. KeySight ICCAP).
• Verilog-A Charge based Compact Model development ( EKV3, CJM ), customization and integration in analog simulators.
• Authored or co-authored 11 journal and 26 conference papers.

 

Starting 2016, I am with Microelectronics Research Group (MRG)/ Institute of Electronic Structure and Laser (IESL)/ Foundation for Research and Technology-Hellas (FORTH) working on development, modeling and characterization of SiC JFETs and GaN HEMTs.

Awards/Acknowledgments:

• Received "Best Paper Award in 48th European Solid-State Device Research Conference (ESSDERC 2018), Sept. 3-6, 2018 Dresden (Germany)"
• Received "Best Paper Award in 41st IEEE International Semiconductor Conference (CAS 2018), Oct. 10-12, 2018 Sinaia (Romania)”

Education

• 2011, M.Sc., School of Electronic and Computer Engineering, Technical University of Crete (TUC), Chania, Greece
• 2006, B.Sc. in Electronic and computer engineering, School of Electronic and Computer Engineering, Technical University of Crete (TUC), Chania, Greece